Fin-type Field Effect Transistors (FinFETs) have attracted much attention due to their excellent performance in suppressing the short channel effect. FIG. 1 shows a perspective view of an existing FinFET device. As shown in FIG. 1, the FinFET comprises: a bulk-Si semiconductor substrate 100; a fin 101 formed on the bulk-Si semiconductor substrate 100; a gate stack 102 across the fin 101, the gate stack 102 comprising, e.g., a gate dielectric layer and a gate electrode layer (not shown); and an isolation layer (e.g. SiO2) 103. In the FinFET, conductive channels are created in three sides (a left side, a right side, and a top side in the figure) of the fin 101, under control of gate electrodes. In other words, portions of the fin 101 under the gate electrodes function as channel regions. A source region and a drain region are located at both sides of each of the channel regions, respectively.
In the example shown in FIG. 1, the FinFET is formed on the bulk-Si semiconductor layer. However, the FinFET can also be formed on other types of substrate, such as a Silicon-on-Insulator (SOI) substrate. Furthermore, the FinFET shown in FIG. 1 is also called a three-gate FET, because the channels are formed in three sides of the fin 101. Alternatively, a two-gate FET may be formed by arranging an isolation layer (e.g. a nitride layer, etc.) between the top side of the fin 101 and the gate stack 102. In such a case, the top side of the fin 101 is not controlled by the gate electrode, and therefore no channel will be created therein.
Although the FinFET provides improved performances in comparison with conventional Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), it also brings some design challenges. In particular, there are generally no limitations on the device widths for the conventional MOSFETs, but the fins of the FinFETs typically need to be of the same height. The fins in different FinFETs need to have the same physical width in order to facilitate photolithographic patterning of the fins.
In other words, the conventional MOSFET provides two parameters, a channel width W and a channel length L, for controlling a conductive current and a cutoff current of the transistor. However, the FinFET only provides one parameter, a length L of the FinFET, for controlling the conductive current and the cutoff current of the transistor. This is because the fin has a fixed height and therefore the channel width is fixed. As a result, for a given length L of the transistor, which defines a ratio between the conductive current and the cutoff current, the conductive current amount from a single fin is fixed.
However, high-performance integrated circuits usually need transistors with varied conductive currents. One way to vary the conductive currents is to change driving capabilities of respective devices by varying fin heights. Layout area will not increase because only vertical dimensions are changed.
However, there has not been any effective way to change the fin heights. Therefore, a new semiconductor manufacturing process is needed for integrating a plurality of semiconductor devices with different device dimensions or fin heights on the same wafer.